This application is related to Japanese Patent Application No. HEI 11(1999)-121760, filed on Apr. 28, 1999 whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to an integrated injection logic (IIL) reset circuit which is used for stably maintaining an initial state of electronic devices immediately after power-up, so as to ensure a reliable initial operation.
2. Description of Related Art
A conventional reset circuit has a construction as shown in FIG. 5. In FIG. 5, when a voltage Vcc is applied to the reset circuit from a power source via a switch S, electric current runs to a capacitor C5 via a resistor 503 and charges the capacitor C5. Thereby a base voltage of a transistor 502 begins to increase. When the base voltage exceeds a threshold voltage, the transistor 502 is turned on. That is, even if the voltage Vcc is applied, in an initial state, the transistor 502 is in a off state and an output of an inverter 501 is conductive, i.e., in a xe2x80x9cLowxe2x80x9d state and a flip-flop circuit 506 is in a reset state. After the voltage Vcc is applied, the base voltage of the transistor 502 is raised by a charge accumulated in the capacitor C5. When the base voltage exceeds a threshold voltage of the transistor 502, the transistor 502 is turned on and the output of the inverter 501 is changed to a cut-off state, i.e., a xe2x80x9cHighxe2x80x9d state. Thereby the flip-flop circuit 506 is released from the reset state and goes into a standby state. Thus a reset period is determined by a time period during which the voltage of the capacitor C5 exceeds to the threshold voltage. Accordingly, if the reset period is set sufficiently longer than a time period necessary for the flip-flop circuit 506 to begin operation, the initial state can be maintained stably after the switch S is turned on.
Another conventional reset circuit is shown in FIG. 6 (see Japanese Unexamined Patent Publication No. SHO 61(1986)-208921, for example). In FIG. 6, in addition to a basic construction in which an output of an inverter 607 is connected to a flip-flop circuit 614, resistors 608, 609 and 612 and transistors 604 and 605 are added. With this construction, a threshold voltage level at which a reset cancellation signal is output is set with respect to a value into which a supply voltage Vcc is divided by the resistors 608, 609 and 612. A reset pulse is generated using a time period required for rise of a power source. Thus, a capacitor is not required at all in this arrangement, and the above reset circuit is formed within a single integrated circuit.
However, these conventional reset circuits have the following drawbacks.
In the reset circuit shown in FIG. 5, the reset pulse may be disturbed by a noise generated outside or inside the circuit and comparable to the threshold voltage for setting the reset or canceling the reset. Furthermore, since the capacitor C5 is required to have a large capacitance, the capacitor C5 must be provided outside the circuit as an attached component. Accordingly, the reset circuit is susceptible to an external noise through external terminals for connecting the capacitor. Also, since resistance exists between grounds of the integrated circuit and the externally attached component and a difference is produced between potential levels of the grounds through operation of the circuit or by an external noise, a wrong reset pulse may be generated. Furthermore, if the rise of the supply voltage at power-up is extremely slow, the charging of the capacitor is completed before reaching an operating voltage of the flip-flop circuit, so that the reset pulse is not generated.
In the reset circuit shown in FIG. 6, the rise time of the power source is utilized for determining the reset time. If the supply voltage reaches an operating voltage within an extremely short period at the power-up, the transistor 605 is saturated in a moment, and the reset state is cancelled before a reset pulse is output. Thus, an effective reset pulse is not generated sufficiently.
The present invention provides a IIL reset circuit comprising an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal, wherein the IIL inverter, when supplied with a constant current to be activated, charges the capacitor through the input terminal and outputs a reset pulse through the output terminal, the reset pulse having a pulse width determined based on a current supplied to the capacitor and a capacitance of the capacitor.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.